1. Field of the Invention
The present invention relates to an I/O (input/output) buffer, and in particular to an I/O buffer circuit which is capable of permitting a voltage level in specific level order when voltage levels of input and output signals are different from each other.
2. Description of the Prior Art
With the development of semiconductor fabrication techniques, a size of a semiconductor device has been reduced, and accordingly a level of power voltage supplied to a semiconductor chip for operating an IC (integrated circuit) has been lowered gradually.
On the other hand, input/output with the conventional semiconductor chip operated in a comparatively high power voltage level is requested continually. In particular, because a semiconductor chip using a core power voltage level and an output power voltage level differently has came into the market, it is required to solve problems caused by difference between an input signal level and an output signal level.
For example, in one semiconductor chip, a core voltage level as 1.8V or 1.5V is used, a voltage level of an output signal is 2.5V or 3.3V, an input/output (hereinafter, it is referred to an I/O) buffer for receiving a 5V signal from a bi-directional I/O node is necessary. In that case, the I/O buffer simultaneously requires a function for permitting an external input signal in a level higher than an output signal level and a function for converting a core signal in a level lower than an output signal level into an output voltage signal level. Recently, various circuits for performing these functions have been presented, and most circuits are for solving problems occurred when an input signal level is higher than an output signal level. First, in order to describe those problems, FIG. 1 illustrates a general I/O buffer circuit, and FIG. 2 illustrates the conventional I/O buffer circuit for solving the problems.
FIG. 1 is an exemplary view illustrating a general I/O buffer circuit.
Hereinafter, the operation of the I/O buffer circuit in FIG. 1 will be described.
First, in a CMOS process, FIG. 1 shows a N-well usage method for implementing a p-mos transistor onto a p-substrate. In order to support a bi-directional I/O, a tri-state buffer for operating an output signal level as a “high” or a “low” state in an output mode (EN: logic “high”) and operating an output node as a high impedance state in an input mode (EN: logic “low”) is mainly used. Herein, when a voltage level of a power terminal (VDDO) connected to a p-mos transistor (MP11) of the last output block determining a level of an output signal is lower than a level of a logic “high” voltage (VDDI), the p-mos transistor (MP11) has to be turned off so as to be in a high impedance state.
However, because the same level voltage (VDDO) with the output signal is applied to a gate of the p-mos transistor (MP11), the p-mos transistor (MP11) is turned on, and accordingly current of a signal applied from an I/O node is leaked to the power terminal (VDDO).
In addition, in most cases, because the N-well is connected to the power terminal (VDDO), forward bias is generated in a drain of the p-mos transistor (MP11), a p-diffusion region forming a source and the N-well as a bulk of the p-mos transistor (MP11), power is supplied to other parts due to current leakage caused by the forward bias, and accordingly a level of the power voltage may be varied.
In order to solve the above-mentioned problem, FIG. 2 illustrates an example of a circuit for floating the N-well bias.
FIG. 2 is an exemplary view illustrating another I/O buffer circuit in accordance with the conventional art.
Hereinafter, the conventional I/O buffer circuit will be described in detail with reference to accompanying drawings.
In a high impedance state for receiving an input signal through an I/O node, a “high” voltage is supplied to a gate of a p-mos transistor (MP21), and a “low” voltage is supplied to a gate of a n-mos transistor (MN21). Herein, a power voltage for determining a voltage level of an output signal is called VDDO, a power voltage for determining a voltage level of an input signal is called VDDI, if the VDDI is higher than the VDDO, because a level of the voltage applied to the gate of the p-mos transistor (MP21) is lower than the VDDI, the p-mos transistor (MP21) is turned on, and accordingly current flows in the VDDO direction. Herein, a p-mos transistor (MP22) performs a function for preventing the above-mentioned problem.
A gate of the p-mos transistor (MP22) is connected to the VDDO, a drain of the p-mos transistor (MP22) is connected to the I/O node. When a level of an input signal supplied to the I/O node is higher than a voltage of the VDDO, the p-mos transistor (MP22) is turned on. Herein, because the VDDI is applied to the gate of the p-mos transistor (MP21) connected to a source of the p-mos transistor (MP22), it is possible to prevent the p-mos transistor (MP21) from being turned on, and accordingly a current path through the p-mos transistor (MP21) is cut off.
In addition, a p-mos transistor (MP23) performs a function for preventing forward bias between a p-diffusion region of the drain of the p-mos transistor (MP21) and a PN-junction of the N-well as the bulk of the p-mos transistor (MP21).
The source of the p-mos transistor (MP22) is connected to a gate of the p-mos transistor (MP23), the VDDO is connected to the source of the p-mos transistor (MP23), and accordingly the N-well as the bulk is connected to the drain of the p-mos transistor (MP23). Accordingly, when the p-mos transistor (MP22) is turned on, the VDDI is applied to the gate of the p-mos transistor (MP23), and accordingly the N-well bias is cut off.
Because the gate of the p-mos transistor (MP23) is commonly connected with the gate of the p-mos transistor (MP21), when only the p-mos transistor (MP21) is turned on, the p-mos transistor (MP23) is turned on, and the VDDO voltage bias is generated in the N-well.
However, when the p-mos transistor (MP21) is turned off, the bias voltage is not applied to the N-well including the p-mos transistor (MP23), the p-mos transistor (MP21) and the p-mos transistor (MP22). In more detail, the N-well bias is floating.
When the p-mos transistor (MP22) is turned on, a n-mos transistor (MN22) performs a function for preventing a high voltage in the VDDI level from being applied to the internal circuit (a circuit using a power voltage lower than the VDDO such as the ND21). In more detail, because a gate of the n-mos transistor (MN22) is connected to the VDDO, a voltage level appliable to the internal side is limited so as to be not higher than the voltage level of the VDDO, and accordingly the internal circuit can be protected. Herein, when a voltage level lower than a VDDO voltage level as an I/O buffer output signal level is used for a voltage level (VDDC) of the internal core, because the p-mos transistor (MP21) can not be totally cut off, a function for changing different voltage level is required. However, the circuit shown in FIG. 2 can not solve the problem of the circuit in FIG. 1 and can not implement a function for increasing a voltage level by changing different voltage level.
As described above, in the conventional c-mos I/O buffer, it is possible to prevent current leakage through a p-mos transistor connected to an I/O node. Herein, when a voltage level lower than a level of a power terminal voltage as an output signal level of an I/O buffer is used as an internal core voltage, because a p-mos transistor connected to the I/O node can not be totally turned off, a function for changing a voltage level is required, however, the conventional art can not satisfy that request.